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XR16V2651
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE
MAY 2007 REV. 1.0.2
GENERAL DESCRIPTION
The XR16V26511 (V2651) is a high performance dual universal asynchronous receiver and transmitter (UART) with 32 byte TX and RX FIFOs. The device operates from 2.25 to 3.6 volts with 5 Volt tolerant inputs and is pin-to-pin and software compatible to Exar's XR16V2551 and XR16L2551. The device includes 2 additional capabilities over the XR16V2650: Intel and Motorola data bus selection and a "PowerSave" mode to further reduce sleep current to a minimum during sleep mode. It supports the Exar's enhanced features of selectable FIFO trigger level, automatic hardware (RTS/CTS) and software flow control, and a complete modem interface. An internal loopback capability allows system diagnostics. Independent programmable fractional baud rate generators are provided in each channel to select data rates up to 16 Mbps at 3.3 Volt and 4X sampling clock. The V2651 is available in 48pin TQFP and 32-pin QFN packages.
NOTE: 1 Covered by U.S. Patent #5,649,122
FEATURES
* 2.25 to 3.6 Volt Operation * 5 Volt Tolerant Inputs * Pin-to-pin compatible to Exar's XR16L2751 in the
48-TQFP package
* Two independent UART channels

Register set identical to 16V2650 Data rate of up to 16 Mbps at 3.3 V, and 12.5 Mbps at 2.5 V with 4X sampling rate Fractional Baud Rate Generator Transmit and Receive FIFOs of 32 bytes Selectable TX and RX FIFO Trigger Levels Automatic Hardware (RTS/CTS) Flow Control Automatic Software (Xon/Xoff) Flow Control Wireless Infrared (IrDA 1.0) Encoder/Decoder Automatic sleep mode with wake-up interrupt Full modem interface

APPLICATIONS
* Portable Appliances * Telecommunication Network Routers * Ethernet Network Routers * Cellular Data Devices * Factory Automation and Process Controls
FIGURE 1. XR16V2651 BLOCK DIAGRAM
* PowerSave Feature reduces sleep current to 15 A * Device Identification and Revision * Crystal oscillator (up to 32MHz) or external clock
(up to 64MHz) input
* 48-TQFP and 32-QFN packages
PwrSave A2:A0 D7:D0 IOR# (VCC) IOW# (R/W#) CSA# (CS#) CSB# (A3) INTA (IRQ#) INTB (logic 0) TXRDYA# TXRDYB# RXRDYA# RXRDYB# Reset (Reset#) 16/68# CLKSEL Intel or Motorola Data Bus Interface
*5 Volt Tolerant Inputs
2.25 to 3.6V VCC GND
UART Channel A UART Regs BRG 32 Byte TX FIFO TX & RX IR ENDEC TXA, RXA, DTRA#, DSRA#, RTSA#, DTSA#, CDA#, RIA#, OP2A#
32 Byte RX FIFO TXB, RXB, DTRB#, DSRB#, RTSB#, CTSB#, CDB#, RIB#, OP2B# XTAL1 XTAL2
UART Channel B (same as Channel A)
Crystal Osc/Buffer
Exar Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com
XR16V2651
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE FIGURE 2. PIN OUT ASSIGNMENT
CTSA# VCC CTSA# VCC
REV. 1.0.2
D4
D3
D2
D1
D5
D0
D4
D5
D3
D2
D1
30
29
D0
26
32
31
28
30
29
26
32
31
28
D6 D7 RXB RXA TXA TXB CSA# CSB#
27
25
27
25
1 2 3 4 5 6 7 8 13 11 16 12 14 10 15 9
24 23
RESET RTSA# INTA INTB A0 A1 A2 16/68# VCC
D6 D7 RXB RXA TXA TXB CS# A3 (CSB#)
1 2 3 4 5 6 7 8 11 13 12 14 RTSB# 15 10 16 9
24 23 22
RESET# (Reset) RTSA# IRQ# NC (INTB) A0 A1 A2 16/68# GND
XR16V2651 32-pin QFN In 16 (Intel) Mode
22 21 20 19 18 17
XR16V2651 32-pin QFN in 68 (Motorola) Mode
21 20 19 18 17
PWRSAVE
GND
43 TXRDYA#
43 TXRDYA#
DSRA#
VCC (IOR#)
PWRSAVE
RTSB#
CTSB#
XTAL2
XTAL1
38 CTSA#
DSRA#
CTSB# 38 CTSA#
XTAL2
40 CDA#
XTAL1
IOW#
R/W#
GND
IOR#
41 RIA#
41 RIA#
42 VCC
42 VCC
37 NC
40 CDA#
39
D5 D6 D7 RXB RXA TXRDYB# TXA TXB OP2B# CSA# CSB# PWRSAVE
1 2 3 4 5 6 7 8 9 10 11 12 IOW# 15 IOR# 19 XTAL1 13 RXRDYB# 18 20 RTSB# 22 CTSB# 23 CDB# 16 RIB# 21 XTAL2 14 GND 17 16/68# 24
36 RESET 35 DTRB# 34 DTRA# 33 RTSA#
39
37 NC
48 D4
47 D3
46 D2
45 D1
44 D0
48 D4
47 D3
46 D2
45 D1
44 D0
D5 D6 D7 RXB RXA TXRDYB# TXA TXB OP2B# CS# A3 PWRSAVE
1 2 3 4 5 6 7 8 9 10 11 12 R/W# 15 XTAL1 13 RXRDYB# 18 NC 19 20 RTSB# 22 CTSB# 23 CDB# 16 XTAL2 14 RIB# 21 GND 17 16/68# 24
36 RESET# 35 DTRB# 34 DTRA# 33 RTSA#
XR16V2651 48-pin TQFP in 16 (Intel) Mode
32 OP2A# 31 RXRDYA# 30 INTA 29 INTB 28 A0 27 A1 26 A2 25 CLKSEL
XR16V2651 48-pin TQFP in 68 (Motorola) Mode
32 OP2A# 31 RXRDYA# 30 IRQ# 29 NC 28 A0 27 A1 26 A2 25 CLKSEL
DSRB#
VCC
DSRB#
GND
ORDERING INFORMATION
PART NUMBER XR16V2651IL32 XR16V2651IM PACKAGE 32-Pin QFN 48-Lead TQFP OPERATING TEMPERATURE RANGE -40C to +85C -40C to +85C DEVICE STATUS Active Active
2
XR16V2651
REV. 1.0.2
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE
PIN DESCRIPTIONS
Pin Description
NAME 32-QFN 48-TQFP TYPE PIN # PIN # DESCRIPTION
DATA BUS INTERFACE A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 IOR# (VCC) 18 19 20 2 1 32 31 30 29 28 27 14 26 27 28 3 2 1 48 47 46 45 44 19 I Address data lines [2:0]. These 3 address lines select one of the internal registers in UART channel A/B during a data bus transaction. Data bus lines [7:0] (bidirectional).
I/O
I
When 16/68# pin is HIGH, the Intel bus interface is selected and this input becomes read strobe (active low). The falling edge instigates an internal read cycle and retrieves the data byte from an internal register pointed by the address lines [A2:A0], puts the data byte on the data bus to allow the host processor to read it on the rising edge. When 16/68# pin is LOW, the Motorola bus interface is selected and this input is not used and should be connected to VCC. When 16/68# pin is HIGH, it selects Intel bus interface and this input becomes write strobe (active low). The falling edge instigates the internal write cycle and the rising edge transfers the data byte on the data bus to an internal register pointed by the address lines. When 16/68# pin is LOW, the Motorola bus interface is selected and this input becomes read (HIGH) and write (LOW) signal. When 16/68# pin is HIGH, this input is chip select A (active low) to enable channel A in the device. When 16/68# pin is LOW, this input becomes the chip select (active low) for the Motorola bus interface. When 16/68# pin is HIGH, this input is chip select B (active low) to enable channel B in the device. When 16/68# pin is LOW, this input becomes address line A3 which is used for channel selection in the Motorola bus interface. Input logic 0 selects channel A and logic 1 selects channel B. When 16/68# pin is HIGH for Intel bus interface, this output becomes channel A interrupt output. The output state is defined by the user through the software setting of MCR[3]. INTA is set to the active mode and OP2A# output to a logic 0 when MCR[3] is set to a logic 1. INTA is set to the three state mode and OP2A# to a logic 1 when MCR[3] is set to a logic 0. See MCR[3]. When 16/68# pin is LOW for Motorola bus interface, this output becomes device interrupt output (active low, open drain). An external pull-up resistor is required for proper operation.
IOW# (R/W#)
12
15
I
CSA# (CS#)
7
10
I
CSB# (A3)
8
11
I
INTA (IRQ#)
22
30
O
3
XR16V2651
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE Pin Description
NAME INTB 32-QFN 48-TQFP TYPE PIN # PIN # 21 29 O DESCRIPTION UART channel B Interrupt output. The output state is defined by the user through the software setting of MCR[3]. INTB is set to the active mode and OP2B# output LOW when MCR[3] is set to a logic 1. INTB is set to the three state mode and OP2B# output HIGH when MCR[3] is set to a logic 0 (default). See MCR[3]. UART channel A Transmitter Ready (active low). The output provides the TX FIFO/ THR status for transmit channel A. See Table 3. If it is not used, leave it unconnected. UART channel A Receiver Ready (active low). This output provides the RX FIFO/ RHR status for receive channel A. See Table 3. If it is not used, leave it unconnected. UART channel B Transmitter Ready (active low). The output provides the TX FIFO/ THR status for transmit channel B. See Table 4. If it is not used, leave it unconnected. UART channel B Receiver Ready (active low). This output provides the RX FIFO/ RHR status for receive channel B. See Table 3. If it is not used, leave it unconnected.
REV. 1.0.2
TXRDYA#
-
43
O
RXRDYA#
-
31
O
TXRDYB#
-
6
O
RXRDYB#
-
18
O
MODEM OR SERIAL I/O INTERFACE TXA 5 7 O UART channel A Transmit Data or infrared encoder data. Standard transmit and receive interface is enabled when MCR[6] = 0. In this mode, the TX signal will be HIGH during reset or idle (no data). Infrared IrDA transmit and receive interface is enabled when MCR[6] = 1. In the Infrared mode, the inactive state (no data) for the Infrared encoder/decoder interface is LOW. If it is not used, leave it unconnected. UART channel A Receive Data or infrared receive data. Normal receive data input must idle HIGH. The infrared receiver pulses typically idles at LOW but can be inverted by software control prior going into the decoder, see MCR[6]. If this pin is not used, tie it to VCC or pull it high via a 100k ohm resistor. UART channel A Request-to-Send (active low) or general purpose output. This output must be asserted prior to using auto RTS flow control, see EFR[6], MCR[1], and IER[6]. UART channel A Clear-to-Send (active low) or general purpose input. It can be used for auto CTS flow control, see EFR[7], and IER[7]. This input should be connected to VCC when not used. UART channel A Data-Terminal-Ready (active low) or general purpose output. If it is not used, leave it unconnected. UART channel A Data-Set-Ready (active low) or general purpose input. This input should be connected to VCC when not used. This input has no effect on the UART. UART channel A Carrier-Detect (active low) or general purpose input. This input should be connected to VCC when not used. This input has no effect on the UART. UART channel A Ring-Indicator (active low) or general purpose input. This input should be connected to VCC when not used. This input has no effect on the UART.
RXA
4
5
I
RTSA#
23
33
O
CTSA#
25
38
I
DTRA# DSRA# CDA# RIA#
-
34 39 40 41
O I I I
4
XR16V2651
REV. 1.0.2
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE
Pin Description
NAME OP2A# 32-QFN 48-TQFP TYPE PIN # PIN # 32 O DESCRIPTION Output Port 2 Channel A - The output state is defined by the user and through the software setting of MCR[3]. INTA is set to the active mode and OP2A# output LOW when MCR[3] is set to a logic 1. INTA is set to the three state mode and OP2A# output HIGH when MCR[3] is set to a logic 0. See MCR[3]. If INTA is used, this output should not be used as a general output else it will disturb the INTA output functionality. UART channel B Transmit Data or infrared encoder data. Standard transmit and receive interface is enabled when MCR[6] = 0. In this mode, the TX signal will be HIGH during reset or idle (no data). Infrared IrDA transmit and receive interface is enabled when MCR[6] = 1. In the Infrared mode, the inactive state (no data) for the Infrared encoder/decoder interface is LOW. If it is not used, leave it unconnected. UART channel B Receive Data or infrared receive data. Normal receive data input must idle HIGH. The infrared receiver pulses typically idles at logic 0 but can be inverted by software control prior going in to the decoder, see MCR[6]. If this pin is not used, tie it to VCC or pull it high via a 100k ohm resistor. UART channel B Request-to-Send (active low) or general purpose output. This port must be asserted prior to using auto RTS flow control, see EFR[6], MCR[1], and IER[6]. UART channel B Clear-to-Send (active low) or general purpose input. It can be used for auto CTS flow control, see EFR[7], and IER[7]. This input should be connected to VCC when not used. UART channel B Data-Terminal-Ready (active low) or general purpose output. If it is not used, leave it unconnected. UART channel B Data-Set-Ready (active low) or general purpose input. This input should be connected to VCC when not used. This input has no effect on the UART. UART channel B Carrier-Detect (active low) or general purpose input. This input should be connected to VCC when not used. This input has no effect on the UART. UART channel B Ring-Indicator (active low) or general purpose input. This input should be connected to VCC when not used. This input has no effect on the UART. Output Port 2 Channel B - The output state is defined by the user and through the software setting of MCR[3]. INTB is set to the active mode and OP2B# output LOW when MCR[3] is set to a logic 1. INTB is set to the three state mode and OP2B# output HIGH when MCR[3] is set to a logic 0. See MCR[3]. If INTB is used, this output should not be used as a general output else it will disturb the INTB output functionality.
TXB
6
8
O
RXB
3
4
I
RTSB#
15
22
O
CTSB#
16
23
I
DTRB# DSRB# CDB# RIB# OP2B#
-
35 20 16 21 9
O I I I O
ANCILLARY SIGNALS XTAL1 XTAL2 PwrSave 10 11 9 13 14 12 I O I Crystal or external clock input. Crystal or buffered clock output. PowerSave (active high). This feature isolates the V2651's data bus interface from the host preventing other bus activities that cause higher power drain during sleep mode. See Sleep Mode with Auto Wake-up and PowerSave Feature section for details.
5
XR16V2651
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE Pin Description
NAME 16/68# 32-QFN 48-TQFP TYPE PIN # PIN # 17 24 I DESCRIPTION Intel or Motorola Bus Select. When 16/68# pin is HIGH, 16 or Intel Mode, the device will operate in the Intel bus type of interface. When 16/68# pin is LOW, 68 or Motorola mode, the device will operate in the Motorola bus type of interface. Baud-Rate-Generator Input Clock Prescaler Select for channel A and B. This input is only sampled during power up or a reset. Connect to VCC for divide by 1 and GND for divide by 4. MCR[7] can override the state of this pin following a reset or initialization. See MCR bit-7 and Figure 5 in the Baud Rate Generator section. When 16/68# pin is HIGH for Intel bus interface, this input becomes RESET (active high). When 16/68# pin is LOW for Motorola bus interface, this input becomes RESET# (active low). A 40 ns minimum active pulse on this pin will reset the internal registers and all outputs of channel A and B. The UART transmitter output will be held HIGH, the receiver input will be ignored and outputs are reset during reset period (see Table 16).
REV. 1.0.2
CLKSEL
-
25
I
RESET (RESET#)
24
36
I
VCC GND GND
26 13 Center Pad
42 17 N/A
Pwr 2.25V to 3.6V power supply. All input pins are 5V tolerant. Pwr Power supply common, ground. Pwr The center pad on the backside of the 32-QFN package is metallic and should be connected to GND on the PCB. The thermal pad size on the PCB should be the approximate size of this center pad and should be solder mask defined. The solder mask opening should be at least 0.0025" inwards from the edge of the PCB thermal pad. No connection.
NC
-
37
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
6
XR16V2651
REV. 1.0.2
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE
1.0 PRODUCT DESCRIPTION The XR16V2651 (V2651) integrates the functions of 2 enhanced 16C550 Universal Asynchronous Receiver and Transmitter (UART). Its features set is compatible to the XR16V2550 and XR16V2650 devices but offers Intel or Motorola data bus interface and PowerSave to isolate the data bus interface during Sleep mode. Hence, the V2651 adds 3 more inputs: 16/68#, PwrSave and CLKSEL pins. Each UART is independently controlled having its own set of device configuration registers. The configuration registers set is 16550 UART compatible for control, status and data transfer. Additionally, each UART channel has 32-bytes of transmit and receive FIFOs, automatic RTS/CTS hardware flow control with hysteresis control, automatic Xon/Xoff and special character software flow control, selectable transmit and receive FIFO trigger levels, infrared encoder and decoder (IrDA ver 1.0), programmable fractional baud rate generator with a prescaler of divide by 1 or 4. The XR16V2651 can operate from 2.25V to 3.6V with 5 volt tolerant inputs. The V2651 is fabricated with an advanced CMOS process. Enhanced Features The V2651 DUART provides a solution that supports 32 bytes of transmit and receive FIFO memory, instead of 16 bytes in the ST16C2550 or one byte in the ST16C2450. The V2651 is designed to work with low supply voltage and high performance data communication systems, that require fast data processing time. Increased performance is realized in the V2651 by the larger transmit and receive FIFOs, FIFO trigger level control, and automatic flow control mechanism. This allows the external processor to handle more networking tasks within a given time. For example, the ST16C2550 with a 16 byte FIFO, unloads 16 bytes of receive data in 1.53 ms (This example uses a character length of 11 bits, including start/stop bits at 115.2 Kbps). This means the external CPU will have to service the receive FIFO at 1.53 ms intervals. However with the 32 byte FIFO in the V2651, the data buffer will not require unloading/loading for 3.06 ms. This increases the service interval giving the external CPU additional time for other applications and reducing the overall UART interrupt servicing time. In addition, the selectable FIFO trigger level interrupt and automatic hardware/software flow control is uniquely provided for maximum data throughput performance especially when operating in a multi-channel system. The combination of the above greatly reduces the CPU's bandwidth requirement, increases performance, and reduces power consumption. Data Bus Interface, Intel or Motorola Type The V2651 provides a single host interface for the 2 UARTs and supports Intel or Motorola microprocessor (CPU) data bus interface. The Intel bus compatible interface allows direct interconnect to Intel compatible type of CPUs using IOR#, IOW# and CSA# or CSB# inputs for data bus operation. The Motorola bus compatible interface instead uses the R/W#, CS# and A3 signals for data bus transactions. Few data bus interface signals change their functions depending on user's selection, see pin description for details. The Intel and Motorola bus interface selection is made through the 16/68# pin. Data Rate The V2651 is capable of operation up to 4 Mbps at 3.3V with 16X internal sampling clock rate, 8 Mbps at 3.3V with 8X sampling clock rate and 16 Mbps at 3.3V with 4X sampling clock rate. The device can operate with an external 24 MHz crystal on pins XTAL1 and XTAL2, or external clock source of up to 64 MHz on XTAL1 pin. With a typical crystal of 14.7456 MHz and through a software option, the user can set the prescaler bit for data rates of up to 3.68 Mbps. The rich feature set of the V2651 is available through the internal registers. Automatic hardware/software flow control, selectable transmit and receive FIFO trigger levels, programmable TX and RX baud rates, infrared encoder/decoder interface, modem interface controls, and a sleep mode are all standard features. Following a power on reset or an external reset, the V2651 is software compatible with previous generation of UARTs, 16C450, 16C550 and 16C650A.
7
XR16V2651
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE 2.0 FUNCTIONAL DESCRIPTIONS 2.1 CPU Interface The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and write transactions. The V2651 data interface supports the Intel compatible types of CPUs and it is compatible to the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data bus transaction. Each bus cycle is asynchronous using CSA/B#, IOR# and IOW# or CS#, R/W# and A3 inputs. Both UART channels share the same data bus for host operations. A typical data bus interconnection for Intel and Motorola mode is shown in Figure 3. FIGURE 3. XR16V2651 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS
REV. 1.0.2
D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 IO R # IO W # UAR T_C SA# UAR T_C SB# U ART_INTA U ART_INTB TXR DYA# RXR D YA# TXR DYB# RXR D YB# UAR T_R ESET
D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 IO R # IO W # C SA# C SB# INTA INTB TXRDYA# R XRD YA# TXRDYB# R XRD YB# RESET
VCC TXA R XA UAR T Channel A D TR A# RTSA# CTSA# DSR A# C DA# RIA# O P2A#
VC C
Serial Interface of R S-232, RS-422
(no connect)
TXB R XB UAR T Channel B D TR B# RTSB# CTSB# DSR B# C DB# RIB# O P2B# (no connect)
Serial Interface of R S-232, RS-422
GND
Intel Data Bus Interconnections
D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 VCC R /W # UAR T_C S# VCC D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 C SB# IO R # IO W # TXB CSA# RXB U ART C hannel B D TR B # R TSB# C TSB# D SRB# CD B# RIB# O P2B#
VC C TXA RXA U ART C hannel A DTRA# R TSA# C TSA# D SRA# C D A# RIA# O P2A#
2.25 to 3.6 Volt VC C
Serial Interface of RS-232, R S-422
(no connect)
UAR T_IR Q # (no connect) TXR DYA # RXR D YA# TXR DYB # RXR D YB# U ART_RESET#
IN TA IN TB TXRD YA# R XRD YA# TXRD YB# R XRD YB# R ESET#
Serial Interface of RS-232, R S-422
(no connect)
G ND
M otorola Data Bus Interconnections
2.2
5-Volt Tolerant Inputs
The V2651 can accept up to 5V inputs even when operating at 3.3V or 2.5V. But note that if the V2651 is operating at 2.5V, its VOH may not be high enough to meet the requirements of the VIH of a CPU or a serial transceiver that is operating at 5V.
8
XR16V2651
REV. 1.0.2
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE
2.3
Device Reset
The RESET input resets the internal registers and the serial interface outputs in both channels to their default state (see Table 16). An active high pulse of longer than 40 ns duration will be required to activate the reset function in the device. 2.4 Device Identification and Revision The XR16V2651 provides a Device Identification code and a Device Revision code to distinguish the part from other devices and revisions. To read the identification code from the part, it is required to set the baud rate generator registers DLL and DLM both to 0x00 (DLD = 0xXX). Now reading the content of the DVID will provide 0x06 for the XR16V2651 and reading the content of DREV will provide the revision of the part; for example, a reading of 0x01 means revision A. 2.5 Channel A and B Selection The UART provides the user with the capability to bi-directionally transfer information between an external CPU and an external serial communication device. During Intel Bus Mode (16/68# pin connected to VCC), a logic 0 on chip select pins, CSA# or CSB#, allows the user to select UART channel A or B to configure, send transmit data and/or unload receive data to/from the UART. Selecting both UARTs can be useful during power up initialization to write to the same internal registers, but do not attempt to read from both UARTs simultaneously. Individual channel select functions are shown in Table 1. TABLE 1: CHANNEL A AND B SELECT IN 16 MODE
CSA# 1 0 1 0 CSB# 1 1 0 0 FUNCTION UART de-selected Channel A selected Channel B selected Channel A and B selected
During Motorola Bus Mode (16/68# pin connected to GND), the package interface pins are configured for connection with Motorola, and other popular microprocessor bus types. In this mode the V2651 decodes an additional address, A3, to select one of the UART ports. The A3 address decode function is used only when in the Motorola Bus Mode. See Table 2. TABLE 2: CHANNEL A AND B SELECT IN 68 MODE
CS# 1 0 0 A3 N/A 0 1 FUNCTION UART de-selected Channel A selected Channel B selected
Each UART channel in the V2651 has a set of enhanced registers for control, monitoring and data loading and unloading. The configuration register set is compatible to those already available in the standard single 16C550 and dual ST16C2550. These registers function as data holding registers (THR/RHR), interrupt status and control registers (ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/ LCR), modem status and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/ DLM/DLD), and a user accessible Scratchpad Register (SPR). Beyond the general 16C2550 features and capabilities, the V2651 offers enhanced feature registers (EFR, Xon/Xoff 1, Xon/Xoff 2) that provide automatic RTS and CTS hardware flow control, and Xon/Xoff software flow control. All the register functions are discussed in full detail later in "Section 3.0, UART INTERNAL REGISTERS" on page 23.
9
XR16V2651
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE 2.6 DMA Mode
REV. 1.0.2
The device does not support direct memory access. The DMA Mode (a legacy term) in this document doesn't mean "direct memory access" but refers to data block transfer operation. The DMA mode affects the state of the RXRDY# A/B and TXRDY# A/B output pins. The transmit and receive FIFO trigger levels provide additional flexibility to the user for block mode operation. The LSR bits 5-6 provide an indication when the transmitter is empty or has an empty location(s) for more data. The user can optionally operate the transmit and receive FIFO in the DMA mode (FCR bit-3=1). When the transmit and receive FIFO are enabled and the DMA mode is disabled (FCR bit-3 = 0), the V2651 is placed in single-character mode for data transmit or receive operation. When DMA mode is enabled (FCR bit-3 = 1), the user takes advantage of block mode operation by loading or unloading the FIFO in a block sequence determined by the selected trigger level. In this mode, the V2651 sets the TXRDY# pin when the transmit FIFO becomes full, and sets the RXRDY# pin when the receive FIFO becomes empty. The following table shows their behavior. Also see Figures 19 through 24. TABLE 3: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE
PINS FCR BIT-0=0 (FIFO DISABLED) FCR BIT-0=1 (FIFO ENABLED) FCR Bit-3 = 0 (DMA Mode Disabled) RXRDY# A/B LOW = 1 byte HIGH = no data TXRDY# A/B LOW = THR empty HIGH = byte in THR LOW = at least 1 byte in FIFO HIGH = FIFO empty LOW = FIFO empty HIGH = at least 1 byte in FIFO FCR Bit-3 = 1 (DMA Mode Enabled) HIGH to LOW transition when FIFO reaches the trigger level, or time-out occurs LOW to HIGH transition when FIFO empties LOW = FIFO has at least 1 empty location HIGH = FIFO is full
2.7
INTA and INTB Outputs
The INTA and INTB interrupt output changes according to the operating mode and enhanced features setup. Table 4 and 5 summarize the operating behavior for the transmitter and receiver. Also see Figures 19 through 24. TABLE 4: INTA AND INTB PINS OPERATION FOR TRANSMITTER
FCR BIT-0 = 0 (FIFO DISABLED) INTA/B Pin LOW = a byte in THR HIGH = THR empty FCR BIT-0 = 1 (FIFO ENABLED) LOW = FIFO above trigger level HIGH = FIFO below trigger level or FIFO empty
TABLE 5: INTA AND INTB PIN OPERATION FOR RECEIVER
FCR BIT-0 = 0 (FIFO DISABLED) INTA/B Pin LOW = no data HIGH = 1 byte FCR BIT-0 = 1 (FIFO ENABLED) LOW = FIFO below trigger level HIGH = FIFO above trigger level
10
XR16V2651
REV. 1.0.2
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE
2.8
Crystal Oscillator or External Clock Input
The V2651 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the oscillator or external clock buffer input with XTAL2 pin being the output. For programming details, see ""Section 2.9, Programmable Baud Rate Generator with Fractional Divisor" on page 11." FIGURE 4. TYPICAL CRYSTAL CONNECTIONS
XTAL1
XTAL2 R1 0-120 (Optional) 1.8432 MHz to 24 MHz
R2 500K - 1M Y1 C1 22-47pF C2 22-47pF
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant, fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100 ppm frequency tolerance) connected externally between the XTAL1 and XTAL2 pins (see Figure 4). The programmable Baud Rate Generator is capable of operating with a crystal oscillator frequency of up to 24 MHz. However, with an external clock input on XTAL1 pin, it can extend its operation up to 64 MHz (16 Mbps serial data rate) at 3.3V with an 4X sampling rate. For further reading on the oscillator circuit please see the Application Note DAN108 on the EXAR web site at http://www.exar.com. 2.9 Programmable Baud Rate Generator with Fractional Divisor Each UART has its own Baud Rate Generator (BRG) with a prescaler for the transmitter and receiver. The prescaler is controlled by a software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide the input crystal or external clock by 1 or 4. The output of the prescaler clocks to the BRG. The BRG further divides this clock by a programmable divisor between 1 and (216 - 0.0625) in increments of 0.0625 (1/16) to obtain a 16X or 8X or 4X sampling clock of the serial data rate. The sampling clock is used by the transmitter for data bit shifting and receiver for data sampling. The BRG divisor (DLL, DLM and DLD registers) defaults to the value of '1' (DLL = 0x01, DLM = 0x00 and DLD = 0x00) upon reset. Therefore, the BRG must be programmed during initialization to the operating data rate. The DLL and DLM registers provide the integer part of the divisor and the DLD register provides the fractional part of the dvisior. Only the four lower bits of the DLD are implemented and they are used to select a value from 0 (for setting 0000) to 0.9375 or 15/16 (for setting 1111). Programming the Baud Rate Generator Registers DLL, DLM and DLD provides the capability for selecting the operating data rate. Table 6 shows the standard data rates available with a 24MHz crystal or external clock at 16X clock rate. If the pre-scaler is used (MCR bit-7 = 1), the output data rate will be 4 times less than that shown in Table 6. At 8X sampling rate, these data rates would double and at 4X sampling rate, they would quadruple. Also, when using 8X or 4X sampling mode, please note that the bit-time will have a jitter
11
XR16V2651
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE
REV. 1.0.2
(+/- 1/16) whenever the DLD is non-zero and is an odd number. When using a non-standard data rate crystal or external clock, the divisor value can be calculated with the following equation(s):
Required Divisor (decimal)= (XTAL1 clock frequency / prescaler) /(serial data rate x 16), with 16X mode, DLD[5:4]='00' Required Divisor (decimal)= (XTAL1 clock frequency / prescaler / (serial data rate x 8), with 8X mode, DLD[5:4] = '01' Required Divisor (decimal)= (XTAL1 clock frequency / prescaler / (serial data rate x 4), with 4X mode, DLD[5:4] = '10'
The closest divisor that is obtainable in the V2651 can be calculated using the following formula: ROUND( (Required Divisor - TRUNC(Required Divisor) )*16)/16 + TRUNC(Required Divisor), where
DLM = TRUNC(Required Divisor) >> 8 DLL = TRUNC(Required Divisor) & 0xFF DLD = ROUND( (Required Divisor-TRUNC(Required Divisor) )*16)
In the formulas above, please note that: TRUNC (N) = Integer Part of N. For example, TRUNC (5.6) = 5. ROUND (N) = N rounded towards the closest integer. For example, ROUND (7.3) = 7 and ROUND (9.9) = 10. A >> B indicates right shifting the value 'A' by 'B' number of bits. For example, 0x78A3 >> 8 = 0x0078. FIGURE 5. BAUD RATE GENERATOR
To Other Channel
DLL, DLM and DLD Registers Prescaler Divide by 1 XTAL1 XTAL2 Crystal Osc/ Buffer Prescaler Divide by 4 MCR Bit-7=0 (default) Fractional Baud Rate Generator Logic MCR Bit-7=1 16X or 8X or 4X Sampling Rate Clock to Transmitter and Receiver
12
XR16V2651
REV. 1.0.2
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE
TABLE 6: TYPICAL DATA RATES WITH A 24 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING
Required Output Data Rate 400 2400 4800 9600 10000 19200 25000 28800 38400 50000 57600 75000 100000 115200 153600 200000 225000 230400 250000 300000 400000 460800 500000 750000 921600 1000000 DIVISOR FOR 16x Clock (Decimal) 3750 625 312.5 156.25 150 78.125 60 52.0833 39.0625 30 26.0417 20 15 13.0208 9.7656 7.5 6.6667 6.5104 6 5 3.75 3.2552 3 2 1.6276 1.5 DIVISOR OBTAINABLE IN V2651 3750 625 312 8/16 156 4/16 150 78 2/16 60 52 1/16 39 1/16 30 26 1/16 20 15 13 9 12/16 7 8/16 6 11/16 6 8/16 6 5 3 12/16 3 4/16 3 2 1 10/16 1 8/16 DLM PROGRAM VALUE (HEX) E 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL PROGRAM VALUE (HEX) A6 71 38 9C 96 4E 3C 34 27 1E 1A 14 F D 9 7 6 6 6 5 3 3 3 2 1 1 DLD PROGRAM VALUE (HEX) 0 0 8 4 0 2 0 1 1 0 1 0 0 0 C 8 B 8 0 0 C 4 0 0 A 8 DATA ERROR RATE (%) 0 0 0 0 0 0 0 0.04 0 0 0.08 0 0 0.16 0.16 0 0.31 0.16 0 0 0 0.16 0 0 0.16 0
2.10
Transmitter
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 32 bytes of FIFO which includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X/8X/4X internal clock. A bit time is 16/8/4 clock periods (see DLD[5:4]). The transmitter sends the start-bit followed by the number of data bits, inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are reported in the Line Status Register (LSR bit-5 and bit-6).
13
XR16V2651
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE 2.10.1 Transmit Holding Register (THR) - Write Only
REV. 1.0.2
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits, parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input register to the transmit FIFO of 32 bytes when FIFO operation is enabled by FCR bit-0. Every time a write operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data location. 2.10.2 Transmitter Operation in non-FIFO Mode The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty. See Figure 6 below. FIGURE 6. TRANSMITTER OPERATION IN NON-FIFO MODE
Data Byte
Transmit Holding Register (THR)
THR Interrupt (ISR bit-1) Enabled by IER bit-1
16X or 8X or 4X Clock ( DLD[5:4] )
Transmit Shift Register (TSR)
M S B
L S B
TXNOFIFO1
2.10.3
Transmitter Operation in FIFO Mode
The host may fill the transmit FIFO with up to 32 bytes of transmit data. The THR empty flag (LSR bit-5) is set whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the amount of data in the FIFO falls below its selected trigger level. The transmit empty interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set when TSR/FIFO becomes empty (See Figure 7 below). FIGURE 7. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE
Transmit Data Byte
Transmit FIFO
THR Interrupt (ISR bit-1) falls below the programmed Trigger Level and then when becomes empty. FIFO is Enabled by FCR bit-0=1
Auto CTS Flow Control (CTS# pin) Flow Control Characters (Xoff1/2 and Xon1/2 Reg.) Auto Software Flow Control
16X or 8X or 4X Clock ( DLD[5:4] )
Transm it Data Shift Register (TSR)
TXFIFO 1
14
XR16V2651
REV. 1.0.2
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE
2.11
Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and 32 bytes of FIFO which includes a byte-wide Receive Holding Register (RHR). The RSR uses the 16X/8X/4X clock (DLD[5:4]) for timing. It verifies and validates every bit on the incoming character in the middle of each data bit. On the falling edge of a start or false start bit, an internal receiver counter starts counting at the 16X/8X/4X clock rate. After 8 clocks (or 4 if 8X or 2 if 4X) the start bit period should be at the center of the start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from assembling a false character. The rest of the data bits and stop bits are sampled and validated in this same manner to prevent false framing. If there were any error(s), they are reported in the LSR register bits 2-4. Upon unloading the receive data byte from RHR, the receive FIFO pointer is bumped and the error tags are immediately updated to reflect the status of the data byte in RHR register. RHR can generate a receive data ready interrupt upon receiving a character or delay until it reaches the FIFO trigger level. Furthermore, data delivery to the host is guaranteed by a receive data ready time-out interrupt when data is not received for 4 word lengths as defined by LCR[1:0] plus 12 bits time. This is equivalent to 3.7-4.6 character times. The RHR interrupt is enabled by IER bit-0. See Figure 8 and Figure 9 below. 2.11.1 Receive Holding Register (RHR) - Read-Only The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift Register. It provides the receive data interface to the host processor. The RHR register is part of the receive FIFO of 32 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data byte are immediately updated in the LSR bits 2-4. FIGURE 8. RECEIVER OPERATION IN NON-FIFO MODE
16X or 8X or 4X C lock ( D LD [5:4] )
R eceive D ata S hift R egister (R S R )
D ata B it V alidation
R eceive D ata C haracters
R eceive D ata B yte and E rrors
E rror Tags in LS R bits 4:2
R eceive D ata H olding R egister (R H R )
R H R Interrupt (IS R bit-2)
R X F IFO 1
15
XR16V2651
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE FIGURE 9. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE
REV. 1.0.2
16X or 8X or 4X Clock ( DLD[5:4] )
Receive Data Shift Register (RSR)
Data Bit Validation
Receive Data Characters
32 bytes by 11-bit wide FIFO
Example : - RX FIFO trigger level selected at 16 bytes (See Note Below) Data falls to 8 Error Tags (32-sets)
Receive Data FIFO
RTS# re-asserts when data falls below the flow control trigger level to restart remote transmitter. Enable by EFR bit-6=1, MCR bit-1. RHR Interrupt (ISR bit-2) programmed for desired FIFO trigger level. FIFO is Enabled by FCR bit-0=1 RTS# de-asserts when data fills above the flow control trigger level to suspend remote transmitter. Enable by EFR bit-6=1, MCR bit-1.
FIFO Trigger=16
Data fills to 24 Error Tags in LSR bits 4:2
Receive Data Byte and Errors
Receive Data
RXFIFO1
2.12
Auto RTS (Hardware) Flow Control
Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS# output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control features is enabled to fit specific application requirement (see Figure 10):
* Enable auto RTS flow control using EFR bit-6. * The auto RTS function must be started by asserting RTS# output pin (MCR bit-1 to logic 1 after it is enabled).
If using the Auto RTS interrupt:
* Enable RTS interrupt through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt when the
RTS# pin makes a transition from low to high: ISR bit-5 will be set to logic 1.
16
XR16V2651
REV. 1.0.2
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE Auto RTS Hysteresis
2.13
The V2651 has a new feature that provides flow control trigger hysteresis while maintaining compatibility with the XR16C850, ST16C650A and ST16C550 family of UARTs. With the Auto RTS function enabled, an interrupt is generated when the receive FIFO reaches the selected RX trigger level. The RTS# pin will not be forced HIGH (RTS off) until the receive FIFO reaches one level above the selected RX trigger level in the trigger table (Table 12). The RTS# pin will return LOW after the RX FIFO is unloaded to one level below the selected RX trigger level in the trigger table (Table 12). Under the above described conditions, the V2651 will continue to accept data until the receive FIFO gets full. The Auto RTS function is initiated when the RTS# output pin is asserted LOW (RTS On). TABLE 7: AUTO RTS (HARDWARE) FLOW CONTROL
RX TRIGGER LEVEL 8 16 24 28 INT PIN ACTIVATION 8 16 24 28 RTS# DE-ASSERTED (HIGH) (CHARACTERS IN RX FIFO) 16 24 28 28 RTS# ASSERTED (LOW) (CHARACTERS IN RX FIFO) 0 8 16 24
2.14
Auto CTS Flow Control
Automatic CTS flow control is used to prevent data overrun to the remote receiver FIFO. The CTS# input is monitored to suspend/restart the local transmitter. The auto CTS flow control feature is selected to fit specific application requirement (see Figure 10):
* Enable auto CTS flow control using EFR bit-7.
If using the Auto CTS interrupt:
* Enable CTS interrupt through IER bit-7 (after setting EFR bit-4). The UART issues an interrupt when the
CTS# pin is de-asserted (HIGH): ISR bit-5 will be set to 1, and UART will suspend transmission as soon as the stop bit of the character in process is shifted out. Transmission is resumed after the CTS# input is reasserted (LOW), indicating more data may be sent.
17
XR16V2651
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE FIGURE 10. AUTO RTS AND CTS FLOW CONTROL OPERATION
Local UART UARTA Receiver FIFO Trigger Reached Auto RTS Trigger Level Transmitter Auto CTS Monitor RXA TXB Remote UART UARTB Transmitter Auto CTS Monitor Receiver FIFO Trigger Reached Auto RTS Trigger Level
REV. 1.0.2
RTSA# TXA
CTSB# RXB
CTSA# Assert RTS# to Begin Transmission 1 ON 2 7 ON 3 8 OFF
RTSB#
RTSA# CTSB# TXB
OFF
10 11
ON ON
Data Starts 4 RXA FIFO INTA (RXA FIFO Interrupt) Receive RX FIFO Data Trigger Level 5
6
Suspend
Restart 9
RTS High Threshold
RTS Low Threshold
12
RX FIFO Trigger Level
RTSCTS1
The local UART (UARTA) starts data transfer by asserting RTSA# (1). RTSA# is normally connected to CTSB# (2) of remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO (4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and continues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unloaded, UARTA monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows (7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its transmit shift register (8). When receive FIFO data in UARTA is unloaded to match the lower threshold of RTS delay (9), UARTA re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until next receive FIFO trigger (12). This same event applies to the reverse direction when UARTA sends data to UARTB with RTSB# and CTSA# controlling the data flow.
18
XR16V2651
REV. 1.0.2
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE
2.15
Auto Xon/Xoff (Software) Flow Control
When software flow control is enabled (See Table 15), the V2651 compares one or two sequential receive data characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed values, the V2651 will halt transmission (TX) as soon as the current character has completed transmission. When a match occurs, the Xoff (if enabled via IER bit-5) flag will be set and the interrupt output pin will be activated. Following a suspension due to a match of the Xoff character, the V2651 will monitor the receive data stream for a match to the Xon-1,2 character. If a match is found, the V2651 will resume operation and clear the flags (ISR bit-4). Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to 0x00. Following reset the user can write any Xon/Xoff value desired for software flow control. Different conditions can be set to detect Xon/Xoff characters (See Table 15) and suspend/resume transmissions. When double 8-bit Xon/Xoff characters are selected, the V2651 compares two consecutive receive characters with two software flow control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above described flow control mechanisms, flow control characters are not placed (stacked) in the user accessible RX data buffer or FIFO. In the event that the receive buffer is overfilling and flow control needs to be executed, the V2651 automatically sends an Xoff message via the serial TX output to the remote modem. The V2651 sends the Xoff-1,2 characters two-character times (= time taken to send two characters at the programmed baud rate) after the receive FIFO crosses the selected trigger level. To clear this condition, the V2651 will transmit the programmed Xon-1,2 characters as soon as receive FIFO is less than one trigger level below the selected trigger level. (See Table 8 below). TABLE 8: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL
RX TRIGGER LEVEL 8 16 24 28 INT PIN ACTIVATION 8 16 24 28 XOFF CHARACTER(S) SENT (CHARACTERS IN RX FIFO) 8* 16* 24* 28* XON CHARACTER(S) SENT (CHARACTERS IN RX FIFO) 0 8 16 24
* After the trigger level is reached, an xoff character is sent after a short span of time (= time required to send 2 characters); for example, after 2.083ms has elapsed for 9600 baud and 10-bit word length setting.
2.16
Special Character Detect
A special character detect feature is provided to detect an 8-bit character when bit-5 is set in the Enhanced Feature Register (EFR). When this character (Xoff2) is detected, it will be placed in the FIFO along with normal incoming RX data. The V2651 compares each incoming receive character with Xoff-2 data. If a match exists, the received data will be transferred to FIFO and ISR bit-4 will be set to indicate detection of special character. Although the Internal Register Table shows Xon, Xoff Registers with eight bits of character information, the actual number of bits is dependent on the programmed word length. Line Control Register (LCR) bits 0-1 defines the number of character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. The word length selected by LCR bits 0-1 also determines the number of bits that will be used for the special character comparison. Bit-0 in the Xon, Xoff Registers corresponds with the LSB bit for the receive character.
19
XR16V2651
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE 2.17 Infrared Mode
REV. 1.0.2
The V2651 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association) version 1.0. The IrDA 1.0 standard that stipulates the infrared encoder sends out a 3/16 of a bit wide HIGH-pulse for each "0" bit in the transmit data stream. This signal encoding reduces the on-time of the infrared LED, hence reduces the power consumption. See Figure 11 below. The infrared encoder and decoder are enabled by setting MCR register bit-6 to a `1'. When the infrared feature is enabled, the transmit data output, TX, idles at logic zero level. Likewise, the RX input assumes an idle level of logic zero from a reset and power up, see Figure 11. Typically, the wireless infrared decoder receives the input pulse from the infrared sensing diode on the RX pin. Each time it senses a light pulse, it returns a HIGH to the data bit stream. However, this is not true with some infrared modules on the market which indicate a LOW by a light pulse. So the V2651 has a provision to invert the input polarity to accommodate this. In this case user can enable MCR bit-2 to invert the input signal.
FIGURE 11. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING
Character Start Data Bits 1 0 1 0 0 1 1 0 Stop 1 1/2 Bit Time 3/16 Bit Time
IrEncoder-1
TX Data
0
Transmit IR Pulse (TX Pin) Bit Time
Receive IR Pulse (RX pin)
Bit Time 1/16 Clock Delay
RX Data
0 Start
1
0
1
0
0
1
1
0
1 Stop
IRdecoder-1
Data Bits Character
20
XR16V2651
REV. 1.0.2
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE Sleep Mode with Wake-Up Indicator and PowerSave Feature
2.18
The V2651 supports low voltage system designs, hence, a sleep mode with auto wake-up and PowerSave feature is included to reduce power consumption when the device is not actively used. 2.18.1 Sleep Mode All of these conditions must be satisfied for the V2651 to enter sleep mode:

no interrupts pending for both channels of the V2651 (ISR bit-0 = 1) sleep mode of both channels are enabled (IER bit-4 = 1) modem inputs are not toggling (MSR bits 0-3 = 0) RX input pins are idling HIGH
The V2651 stops its crystal oscillator to conserve power in the sleep mode. User can check the XTAL2 pin for no clock output as an indication that the device has entered the sleep mode. The V2651 resumes normal operation by any of the following when PowerSave mode is disabled:

a receive data start bit transition (HIGH to LOW) a data byte is loaded to the transmitter, THR or FIFO a change of logic state on any of the modem or general purpose serial inputs: CTS#, DSR#, CD#, RI#
If the sleep mode is enabled and the V2651 is awakened by one of the conditions described above, an interrupt is issued by the V2651 to signal to the CPU that it is awake. The lower nibble of the interrupt source register (ISR) will read a value of 0x1 for this interrupt and reading the ISR clears this interrupt. Since the same value (0x1) is also used to indicate no pending interrupt, users should exercise caution while using the sleep mode. The V2651 will return to the sleep mode automatically after all interrupting conditions have been serviced and cleared. If the V2651 is awakened by the modem inputs, a read to the MSR is required to reset the modem inputs. In any case, the sleep mode will not be entered while an interrupt is pending from channel A or B. The V2651 will stay in the sleep mode of operation until it is disabled by setting IER bit-4 to a logic 0. A word of caution: owing to the starting up delay of the crystal oscillator after waking up from sleep mode, the first few receive characters may be lost. The number of characters lost during the restart also depends on your operating data rate. More characters are lost when operating at higher data rate. Also, it is important to keep RX A/B inputs idling HIGH or "marking" condition during sleep mode to avoid receiving a "break" condition upon the restart. This may occur when the external interface transceivers (RS-232, RS-422 or another type) are also put to sleep mode and cannot maintain the "marking" condition. To avoid this, the designer can use a 47k-100k ohm pull-up resistor on the RXA and RXB pins. 2.18.2 PowerSave Feature If the address lines, data bus lines, IOW#, IOR#, CSA#, CSB#, and modem input lines remain steady when the V2651 is in sleep mode, the maximum current will be in the microamp range as specified in the DC Electrical Characteristics on page 38. If the input lines are floating or are toggling while the V2651 is in sleep mode, the current can be up to 100 times more. If not using the PowerSave feature, then an external buffer would be required to keep the address and data bus lines from toggling or floating to achieve the low current. But if the PowerSave feature is enabled (pin 12 connected to VCC), this will eliminate the need for an external buffer by internally isolating the address, data and control signals (see Figure 1 on page 1) from other bus activities that could cause wasteful power drain. The V2651 enters PowerSave mode when the PwrSave pin is connected to VCC and the V2651 is in sleep mode (see Sleep Mode section above). Since PowerSave mode isolates the address, data and control signals, the device will wake-up by:

a receive data start bit transition (HIGH to LOW) a change of logic state on any of the modem or general purpose serial inputs: CTS#, DSR#, CD#, RI#
The V2651 will return to the PowerSave mode automatically after a read to the MSR (to reset the modem inputs) and all interrupting conditions have been serviced and cleared. The V2651 will stay in the PowerSave mode of operation until it is disabled by setting IER bit-4 to a logic 0 and/or the PwrSave pin is connected to GND.
21
XR16V2651
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE 2.19 Internal Loopback
REV. 1.0.2
The V2651 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally. Figure 12 shows how the modem port signals are re-configured. Transmit data from the transmit shift register output is internally routed to the receive shift register input allowing the system to receive the same data that it was sending. The TX, RTS# and DTR# pins are held while the CTS#, DSR# CD# and RI# inputs are ignored. Caution: the RX input pin must be held HIGH during loopback test else upon exiting the loopback test the UART may detect and report a false "break" signal. Also, Auto RTS/CTS flow control is not supported during internal loopback.
FIGURE 12. INTERNAL LOOP BACK IN CHANNEL A AND B
VCC Transmit Shift Register (THR/FIFO) MCR bit-4=1 Internal Data Bus Lines and Control Signals Receive Shift Register (RHR/FIFO) VCC RTS# Modem / General Purpose Control Logic RTSA#/RTSB# TXA/TXB
RXA/RXB
CTS# VCC DTR# DSR# OP1# RI# VCC OP2# CD#
CTSA#/CTSB# DTRA#/DTRB#
DSRA#/DSRB# RIA#/RIB# OP2A#/OP2B#
CDA#/CDB#
22
XR16V2651
REV. 1.0.2
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE
3.0 UART INTERNAL REGISTERS Each of the UART channel in the V2651 has its own set of configuration registers selected by address lines A0, A1 and A2 with CSA# or CSB# selecting the channel. The complete register set is shown on Table 9 and Table 10. TABLE 9: UART CHANNEL A AND B UART INTERNAL REGISTERS
ADDRESSES A2 A1 A0 REGISTER 16C550 COMPATIBLE REGISTERS 0 0 0 0 0 0 0 0 0 1 1 1 1 00 00 01 10 00 01 01 10 11 00 01 10 11 RHR - Receive Holding Register THR - Transmit Holding Register DLL - Divisor LSB DLM - Divisor MSB DLD - Divisor Fractional DREV - Device Revision Code DVID - Device Identification Code IER - Interrupt Enable Register ISR - Interrupt Status Register FCR - FIFO Control Register LCR - Line Control Register MCR - Modem Control Register LSR - Line Status Register MSR - Modem Status Register SPR - Scratch Pad Register ENHANCED REGISTERS 0 1 1 1 1 10 00 01 10 11 EFR - Enhanced Function Register Xon-1 - Xon Character 1 Xon-2 - Xon Character 2 Xoff-1 - Xoff Character 1 Xoff-2 - Xoff Character 2 Read/Write Read/Write Read/Write Read/Write Read/Write LCR = 0xBF Read-only Write-only Read/Write Read/Write Read/Write Read-only Read-only Read/Write Read-only Write-only Read/Write Read/Write Read-only Read-only Read/Write LCR 0xBF LCR[7] = 0 READ/WRITE COMMENTS
LCR[7] = 1, LCR 0xBF LCR[7] = 1, LCR 0xBF, EFR[4] = 1 DLL, DLM = 0x00, LCR[7] = 1, LCR 0xBF LCR[7] = 0 LCR 0xBF
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TABLE 10: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS A2-A0 REG NAME READ/ WRITE BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0 COMMENT
16C550 Compatible Registers 000 000 001 RHR THR IER RD WR RD/WR Bit-7 Bit-7 0/ Bit-6 Bit-6 0/ Bit-5 Bit-5 0/ Xoff Int. Enable 0/ INT Source Bit-5 0/ Bit-4 Bit-4 0/ Sleep Mode Enable 0/ INT Source Bit-4 0/ Bit-3 Bit-3 Bit-2 Bit-2 Bit-1 Bit-1 Bit-0 Bit-0 LCR[7]=0
CTS Int. RTS Int. Enable Enable 010 ISR RD FIFOs FIFOs Enabled Enabled
Modem RX Line TX RX Stat. Int. Stat. Empty Data Enable Int. Int Int. Enable Enable Enable INT Source Bit-3 INT INT INT Source Source Source Bit-2 Bit-1 Bit-0
LCR 0xBF DMA Mode Enable Parity Enable TX FIFO Reset Stop Bits OP1# IR Invert RX Parity Error Delta RI# Bit-2 RX FIFO Reset FIFOs Enable
010
FCR
WR
RX FIFO RX FIFO Trigger Trigger
TX FIFO TX FIFO Trigger Trigger Set Parity 0/ Even Parity
011
LCR
RD/WR
Divisor Enable 0/ BRG Prescaler
Set TX Break 0/
Word Word Length Length Bit-1 Bit-0 RTS# DTR# Output Output Control Control
100
MCR
RD/WR
Internal OP2#/INT Lopback Output IR Mode XonAny Enable Enable ENable THR & TSR Empty RI# Input Bit-6 THR Empty RX Break RX Framing Error
101
LSR
RD
RX FIFO Global Error CD# Input Bit-7
RX Overrun Error Delta DSR# Bit-1
RX Data LCR 0xBF Ready Delta CTS# Bit-0
110 111
MSR SPR
RD RD/WR
DSR# Input Bit-5
CTS# Input Bit-4
Delta CD# Bit-3
Baud Rate Generator Divisor 000 001 010 DLL DLM DLD RD/WR RD/WR RD/WR Bit-7 Bit-7 0 Bit-6 Bit-6 0 Bit-5 Bit-5 Bit-4 Bit-4 Bit-3 Bit-3 Bit-3 Bit-2 Bit-2 Bit-2 Bit-1 Bit-1 Bit-1 Bit-0 Bit-0 Bit-0 LCR[7]=1 LCR 0xBF LCR[7]=1 LCR 0xBF EFR[4] = 1 LCR[7]=1 LCR 0xBF DLL=0x00 DLM=0x00
4X Mode 8X Mode
000 001
DREV DVID
RD RD
Bit-7 0
Bit-6 0
Bit-5 0
Bit-4 0
Bit-3 0
Bit-2 1
Bit-1 1
Bit-0 0
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HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE
TABLE 10: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS A2-A0 REG NAME READ/ WRITE BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0 COMMENT
Enhanced Registers 010 EFR RD/WR Auto CTS Enable Auto RTS Enable Special Char Select
Enable IER [7:4], ISR [5:4], FCR[5:4], MCR[7:5], DLD
Software Flow Cntl Bit-3 Bit-3 Bit-3 Bit-3 Bit-3
Software Flow Cntl Bit-2 Bit-2 Bit-2 Bit-2 Bit-2
Software Flow Cntl Bit-1 Bit-1 Bit-1 Bit-1 Bit-1
Software Flow Cntl Bit-0 Bit-0 Bit-0 Bit-0 Bit-0 LCR=0xBF
100 101 110 111
XON1 RD/WR XON2 RD/WR XOFF1 RD/WR XOFF2 RD/WR
Bit-7 Bit-7 Bit-7 Bit-7
Bit-6 Bit-6 Bit-6 Bit-6
Bit-5 Bit-5 Bit-5 Bit-5
Bit-4 Bit-4 Bit-4 Bit-4
4.0 INTERNAL REGISTER DESCRIPTIONS 4.1 4.2 4.3 Receive Holding Register (RHR) - Read- Only Transmit Holding Register (THR) - Write-Only Interrupt Enable Register (IER) - Read/Write SEE"RECEIVER" ON PAGE 15. SEE"TRANSMITTER" ON PAGE 13. The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR). 4.3.1 IER versus Receive FIFO Interrupt Mode Operation When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts (see ISR bits 2 and 3) status will reflect the following: A. The receive data available interrupts are issued to the host when the FIFO has reached the selected trigger level. It will be cleared when the FIFO drops below the selected trigger level. B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register status bit and the interrupt will be cleared when the FIFO drops below the trigger level. C. The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to the receive FIFO. It is reset when the FIFO is empty.
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HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE 4.3.2 IER versus Receive/Transmit FIFO Polled Mode Operation
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When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16V2651 in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). A. LSR BIT-0 indicates there is data in RHR or RX FIFO. B. LSR BIT-1 indicates an overrun error has occurred and that data in the FIFO may not be valid. C. LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any. D. LSR BIT-5 indicates THR is empty. E. LSR BIT-6 indicates when both the transmit FIFO and TSR are empty. F. LSR BIT-7 indicates a data error in at least one character in the RX FIFO. IER[0]: RHR Interrupt Enable The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when the receive FIFO has reached the selected trigger level in the FIFO mode.
* Logic 0 = Disable the receive data ready interrupt (default). * Logic 1 = Enable the receiver data ready interrupt.
IER[1]: THR Interrupt Enable This bit enables the Transmit Ready interrupt which is issued whenever the THR becomes empty in the nonFIFO mode or when data in the FIFO falls below the selected trigger level in the FIFO mode. If the THR is empty when this bit is enabled, an interrupt will be generated.
* Logic 0 = Disable Transmit Ready interrupt (default). * Logic 1 = Enable Transmit Ready interrupt.
IER[2]: Receive Line Status Interrupt Enable If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller about the error status of the current data byte in FIFO. LSR bit-1 generates an interrupt immediately when the character has been received. LSR bits 2-4 generate an interrupt when the character with errors is read out of the FIFO.
* Logic 0 = Disable the receiver line status interrupt (default). * Logic 1 = Enable the receiver line status interrupt.
IER[3]: Modem Status Interrupt Enable
* Logic 0 = Disable the modem status register interrupt (default). * Logic 1 = Enable the modem status register interrupt.
IER[4]: Sleep Mode Enable (requires EFR bit-4 = 1)
* Logic 0 = Disable Sleep Mode (default). * Logic 1 = Enable Sleep Mode. See Sleep Mode section for further details.
IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1)
* Logic 0 = Disable the software flow control, receive Xoff interrupt (default). * Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for
details.
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IER[6]: RTS# Output Interrupt Enable (requires EFR bit-4=1)
* Logic 0 = Disable the RTS# interrupt (default). * Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition
from low to high. IER[7]: CTS# Input Interrupt Enable (requires EFR bit-4=1)
* Logic 0 = Disable the CTS# interrupt (default). * Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition from
low to high. 4.4 Interrupt Status Register (ISR) - Read-Only The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt Source Table, Table 11, shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources associated with each of these interrupt levels. 4.4.1 Interrupt Generation:
* LSR is by any of the LSR bits 1, 2, 3 and 4. * RXRDY is by RX trigger level. * RXRDY Time-out is by a 4-char plus 12 bits delay timer. * TXRDY is by TX trigger level or TX FIFO empty. * MSR is by any of the MSR bits 0, 1, 2 and 3. * Receive Xoff/Special character is by detection of a Xoff or Special character. * CTS# is when its transmitter toggles the input pin (from LOW to HIGH) during auto CTS flow control. * RTS# is when its receiver toggles the output pin (from LOW to HIGH) during auto RTS flow control. * Wake-up Indicator is when the UART comes out of sleep mode.
4.4.2 Interrupt Clearing:
* LSR interrupt is cleared by a read to the LSR register. * RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level. * RXRDY Time-out interrupt is cleared by reading RHR. * TXRDY interrupt is cleared by a read to the ISR register or writing to THR. * MSR interrupt is cleared by a read to the MSR register. * Xoff interrupt is cleared by a read to ISR or when Xon character(s) is received. * Special character interrupt is cleared by a read to ISR or after the next character is received. * RTS# and CTS# flow control interrupts are cleared by a read to the MSR register. * Wake-up Indicator is cleared by a read to the ISR register.
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]
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TABLE 11: INTERRUPT SOURCE AND PRIORITY LEVEL
PRIORITY LEVEL 1 2 3 4 5 6 7 BIT-5 0 0 0 0 0 0 1 0 ISR REGISTER STATUS BITS BIT-4 0 0 0 0 0 1 0 0 BIT-3 0 1 0 0 0 0 0 0 BIT-2 1 1 1 0 0 0 0 0 BIT-1 1 0 0 1 0 0 0 0 BIT-0 0 0 0 0 0 0 0 1 LSR (Receiver Line Status Register) RXRDY (Receive Data Time-out) RXRDY (Received Data Ready) TXRDY (Transmit Ready) MSR (Modem Status Register) RXRDY (Received Xoff or Special character) CTS#, RTS# change of state None (default) or Wake-up Indicator SOURCE OF INTERRUPT
ISR[0]: Interrupt Status
* Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
* Logic 1 = No interrupt pending (default condition) or the device has come out of sleep mode.
ISR[3:1]: Interrupt Status These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source Table 11). ISR[4]: Xoff/Xon or Special Character Interrupt Status This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that the receiver detected a data match of the Xoff character(s). If this is an Xoff/Xon interrupt, it can be cleared by a read to the ISR. If it is a special character interrupt, it can be cleared by reading ISR or it will automatically clear after the next character is received. ISR[5]: RTS#/CTS# Interrupt Status This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-5 indicates that the CTS# or RTS# has been deasserted. ISR[7:6]: FIFO Enable Status These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are enabled. 4.5 FIFO Control Register (FCR) - Write-Only This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and select the DMA mode. The DMA, and FIFO modes are defined as follows: FCR[0]: TX and RX FIFO Enable
* Logic 0 = Disable the transmit and receive FIFO (default). * Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
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FCR[1]: RX FIFO Reset This bit is only active when FCR bit-0 is a `1'.
* Logic 0 = No receive FIFO reset (default) * Logic 1 = Reset the receive FIFO pointers (the receive shift register is not cleared or altered). This bit will
return to a logic 0 after resetting the FIFO. FCR[2]: TX FIFO Reset This bit is only active when FCR bit-0 is a `1'.
* Logic 0 = No transmit FIFO reset (default). * Logic 1 = Reset the transmit FIFO pointers (the transmit shift register is not cleared or altered). This bit will
return to a logic 0 after resetting the FIFO. FCR[3]: DMA Mode Select Controls the behavior of the TXRDY# and RXRDY# pins. See DMA operation section for details.
* Logic 0 = Normal Operation (default). * Logic 1 = DMA Mode.
FCR[5:4]: Transmit FIFO Trigger Select (requires EFR bit-4=1) (logic 0 = default, TX trigger level = 1) These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that the FIFO did not get filled over the trigger level on last re-load. Table 12 below shows the selections. EFR bit-4 must be set to `1' before these bits can be accessed. FCR[7:6]: Receive FIFO Trigger Select (logic 0 = default, RX trigger level =1) These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when the number of the characters in the FIFO crosses the trigger level. Table 12 shows the complete selections. Whichever selection is made last applies to both the RX and TX side. TABLE 12: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION
FCR BIT-7 FCR BIT-6 FCR BIT-5 0 0 1 1 0 0 1 1 0 1 0 1 FCR
BIT-4
RECEIVE TRIGGER LEVEL
TRANSMIT TRIGGER LEVEL 16 8 24 30
0 1 0 1 8 16 24 28
4.6
Line Control Register (LCR) - Read/Write
The Line Control Register is used to specify the asynchronous data communication format. The word or character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register.
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HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE LCR[1:0]: TX and RX Word Length Select These two bits specify the word length to be transmitted or received.
BIT-1 0 0 1 1 BIT-0 0 1 0 1 WORD LENGTH 5 (default) 6 7 8
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LCR[2]: TX and RX Stop-bit Length Select The length of stop bit is specified by this bit in conjunction with the programmed word length.
BIT-2 0 1 1 WORD
LENGTH
STOP BIT LENGTH (BIT TIME(S)) 1 (default) 1-1/2 2
5,6,7,8 5 6,7,8
LCR[3]: TX and RX Parity Select Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data integrity check. See Table 13 for parity selection summary below.
* Logic 0 = No parity. * Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received. LCR[4]: TX and RX Parity Select If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR bit-4 selects the even or odd parity format.
* Logic 0 = ODD Parity is generated by forcing an odd number of logic 1's in the transmitted character. The
receiver must be programmed to check the same format (default).
* Logic 1 = EVEN Parity is generated by forcing an even number of logic 1's in the transmitted character. The
receiver must be programmed to check the same format. LCR[5]: TX and RX Parity Select If the parity bit is enabled, LCR BIT-5 selects the forced parity format.
* LCR BIT-5 = logic 0, parity is not forced (default). * LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive
data.
* LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive
data.
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LCR BIT-5 LCR BIT-4 LCR BIT-3 X 0 0 1 1 X 0 1 0 1 0 1 1 1 1 PARITY SELECTION No parity Odd parity Even parity Force parity to mark, HIGH Force parity to space, LOW
LCR[6]: Transmit Break Enable When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a "space", LOW state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.
* Logic 0 = No TX break condition (default). * Logic 1 = Forces the transmitter output (TX) to a "space", LOW, for alerting the remote receiver of a line
break condition. LCR[7]: Baud Rate Divisors Enable Baud rate generator divisor (DLL, DLM and DLD) enable.
* Logic 0 = Data registers are selected (default). * Logic 1 = Divisor latch registers are selected.
4.7 Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs. MCR[0]: DTR# Output The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a general purpose output.
* Logic 0 = Force DTR# output HIGH (default). * Logic 1 = Force DTR# output LOW.
MCR[1]: RTS# Output The RTS# pin is a modem control output and may be used for automatic hardware flow control by enabled by EFR bit-6. If the modem interface is not used, this output may be used as a general purpose output.
* Logic 0 = Force RTS# HIGH (default). * Logic 1 = Force RTS# LOW.
MCR[2]: IrDA RX Inversion or OP#1 (legacy term) When Infrared mode is enabled (MCR[6]=1 and EFR[4]=1), this bit selects the idle state of the encoded IrDA data. In internal loopback mode, this bit functions like the OP1# in the 16C550.
* Logic 0 = Select RX input as active-low encoded IrDA data (Idle state will be low) (default). * Logic 1 = Select RX input as active-high encoded IrDA data (Idle state will be high).
In the Internal Loopback Mode, this bit controls the state of the modem input RI# bit in the MSR register as shown in Figure 12.
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HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE MCR[3]: OP2# Output / INT Output Enable This bit enables or disables the operation of INT, interrupt output. If INT output is not used, OP2# can be used as a general purpose output. Also, if 16/68# pin selects Motorola bus interface mode, this bit must be set to logic 0.
REV. 1.0.2
* Logic 0 = INT (A-B) outputs disabled (three state mode) and OP2# output set HIGH(default). * Logic 1 = INT (A-B) outputs enabled (active mode) and OP2# output set LOW.
MCR[4]: Internal Loopback Enable
* Logic 0 = Disable loopback mode (default). * Logic 1 = Enable local loopback mode, see loopback section and Figure 12.
MCR[5]: Xon-Any Enable (requires EFR bit-4=1)
* Logic 0 = Disable Xon-Any function (default). * Logic 1 = Enable Xon-Any function. In this mode, any RX character received will resume transmit operation.
The RX character will be loaded into the RX FIFO, unless the RX character is an Xon or Xoff character and the V2651 is programmed to use the Xon/Xoff flow control. MCR[6]: Infrared Encoder/Decoder Enable (requires EFR bit-4=1)
* Logic 0 = Enable the standard modem receive and transmit input/output interface (default). * Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. The TX/RX output/input are routed to the
infrared encoder/decoder. The data input and output levels conform to the IrDA infrared interface requirement. While in this mode, the infrared TX output will be idling LOW. SEE"INFRARED MODE" ON PAGE 20. MCR[7]: Clock Prescaler Select (requires EFR bit-4=1)
* Logic 0 = Divide by one. The input clock from the crystal or external clock is fed directly to the Programmable
Baud Rate Generator without further modification, i.e., divide by one (default).
* Logic 1 = Divide by four. The prescaler divides the input clock from the crystal or external clock by four and
feeds it to the Programmable Baud Rate Generator, hence, data rates become one forth. 4.8 Line Status Register (LSR) - Read Only This register provides the status of data transfers between the UART and the host. LSR[0]: Receive Data Ready Indicator
* Logic 0 = No data in receive holding register or FIFO (default). * Logic 1 = Data has been received and is saved in the receive holding register or FIFO.
LSR[1]: Receiver Overrun Error Flag
* Logic 0 = No overrun error (default). * Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens
when additional data arrives while the FIFO is full. In this case the previous data in the receive shift register is overwritten. Note that under this condition the data byte in the receive shift register is not transferred into the FIFO, therefore the data in the FIFO is not corrupted by the error. LSR[2]: Receive Data Parity Error Tag
* Logic 0 = No parity error (default). * Logic 1 = Parity error. The receive character in RHR does not have correct parity information and is suspect.
This error is associated with the character available for reading in RHR.
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LSR[3]: Receive Data Framing Error Tag
* Logic 0 = No framing error (default). * Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with
the character available for reading in RHR. LSR[4]: Receive Break Error Tag
* Logic 0 = No break condition (default). * Logic 1 = The receiver received a break signal (RX was LOW for at least one character frame time). In the
FIFO mode, only one break character is loaded into the FIFO. LSR[5]: Transmit Holding Register Empty Flag This bit is the Transmit Holding Register Empty indicator. The THR bit is set to a logic 1 when the last data byte is transferred from the transmit holding register to the transmit shift register. The bit is reset to logic 0 concurrently with the data loading to the transmit holding register by the host. In the FIFO mode this bit is set when the transmit FIFO is empty, it is cleared when the transmit FIFO contains at least 1 byte. LSR[6]: THR and TSR Empty Flag This bit is set to a logic 1 whenever the transmitter goes idle. It is set to logic 0 whenever either the THR or TSR contains a data character. In the FIFO mode this bit is set to a logic 1 whenever the transmit FIFO and transmit shift register are both empty. LSR[7]: Receive FIFO Data Error Flag
* Logic 0 = No FIFO error (default). * Logic 1 = A global indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error
or break indication is in the FIFO data. This bit clears when there is no more error(s) in any of the bytes in the RX FIFO. 4.9 Modem Status Register (MSR) - Read Only This register provides the current state of the modem interface input signals. Lower four bits of this register are used to indicate the changed information. These bits are set to a logic 1 whenever a signal from the modem changes state. These bits may be used for general purpose inputs when they are not used with modem signals. MSR[0]: Delta CTS# Input Flag
* Logic 0 = No change on CTS# input (default). * Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3). MSR[1]: Delta DSR# Input Flag
* Logic 0 = No change on DSR# input (default). * Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3). MSR[2]: Delta RI# Input Flag
* Logic 0 = No change on RI# input (default). * Logic 1 = The RI# input has changed from a LOW to HIGH, ending of the ringing signal. A modem status
interrupt will be generated if MSR interrupt is enabled (IER bit-3).
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HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE MSR[3]: Delta CD# Input Flag
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* Logic 0 = No change on CD# input (default). * Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem
status interrupt will be generated if MSR interrupt is enabled (IER bit-3). MSR[4]: CTS Input Status CTS# pin may function as automatic hardware flow control signal input if it is enabled and selected by Auto CTS (EFR bit-7). Auto CTS flow control allows starting and stopping of local data transmissions based on the modem CTS# signal. A HIGH on the CTS# pin will stop UART transmitter as soon as the current character has finished transmission, and a LOW will resume data transmission. Normally MSR bit-4 bit is the complement of the CTS# input. However in the loopback mode, this bit is equivalent to the RTS# bit in the MCR register. The CTS# input may be used as a general purpose input when the modem interface is not used. MSR[5]: DSR Input Status Normally this bit is the complement of the DSR# input. In the loopback mode, this bit is equivalent to the DTR# bit in the MCR register. The DSR# input may be used as a general purpose input when the modem interface is not used. MSR[6]: RI Input Status Normally this bit is the complement of the RI# input. In the loopback mode this bit is equivalent to bit-2 in the MCR register. The RI# input may be used as a general purpose input when the modem interface is not used. MSR[7]: CD Input Status Normally this bit is the complement of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the MCR register. The CD# input may be used as a general purpose input when the modem interface is not used. 4.10 Scratch Pad Register (SPR) - Read/Write This is a 8-bit general purpose register for the user to store temporary data. The content of this register is preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle. 4.11 Baud Rate Generator Registers (DLL, DLM and DLD) - Read/Write These registers make-up the value of the baud rate divisor. The concatenation of the contents of DLM and DLL is a 16-bit value is then added to DLD[3:0]/16 to achieve the fractional baud rate divisor. DLD must be enabled via EFR bit-4 before it can be accessed. SEE"PROGRAMMABLE BAUD RATE GENERATOR WITH FRACTIONAL DIVISOR" ON PAGE 11. DLD[5:4]: Sampling Rate Select These bits select the data sampling rate. By default, the data sampling rate is 16X. The maximum data rate will double if the 8X mode is selected and will quadruple if the 4X mode is selected. See Table 14 below. TABLE 14: SAMPLING RATE SELECT
DLD[5] 0 0 1 DLD[4] 0 1 X SAMPLING RATE 16X 8X 4X
DLD[7:6]: Reserved 4.12 Device Identification Register (DVID) - Read Only This register contains the device ID (0x06 for XR16V2651). Prior to reading this register, DLL and DLM should be set to 0x00 (DLD = 0xXX).
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4.13
Device Revision Register (DREV) - Read Only
This register contains the device revision information. For example, 0x01 means revision A. Prior to reading this register, DLL and DLM should be set to 0x00 (DLD = 0xXX). 4.14 Enhanced Feature Register (EFR) Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive character software flow control selection (see Table 15). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before programming a new setting. EFR[3:0]: Software Flow Control Select Single character and dual sequential characters software flow control is supported. Combinations of software flow control can be selected by programming these bits. TABLE 15: SOFTWARE FLOW CONTROL FUNCTIONS
EFR BIT-3 CONT-3 0 0 1 0 1 X X X 1 0 1 0 EFR BIT-2 CONT-2 0 0 0 1 1 X X X 0 1 1 0 EFR BIT-1 CONT-1 0 X X X X 0 1 0 1 1 1 1 EFR BIT-0 CONT-0 0 X X X X 0 0 1 1 1 1 1 TRANSMIT AND RECEIVE SOFTWARE FLOW CONTROL No TX and RX flow control (default and reset) No transmit flow control Transmit Xon1, Xoff1 Transmit Xon2, Xoff2 Transmit Xon1 and Xon2, Xoff1 and Xoff2 No receive flow control Receiver compares Xon1, Xoff1 Receiver compares Xon2, Xoff2 Transmit Xon1, Xoff1 Receiver compares Xon1 or Xon2, Xoff1 or Xoff2 Transmit Xon2, Xoff2 Receiver compares Xon1 or Xon2, Xoff1 or Xoff2 Transmit Xon1 and Xon2, Xoff1 and Xoff2 Receiver compares Xon1 and Xon2, Xoff1 and Xoff2 No transmit flow control Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
EFR[4]: Enhanced Function Bits Enable Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, FCR bits 4-5, MCR bits 5-7, and DLD to be modified. After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the new values. This feature prevents legacy software from altering or overwriting the enhanced functions once set. Normally, it is recommended to leave it enabled, logic 1.
* Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, FCR bits 4-5, MCR bits 57, and DLD are saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 4-5, MCR bits 5-7, and DLD are set to a logic 0 to be compatible with ST16C550 mode (default).
* Logic 1 = Enables the above-mentioned register bits to be modified by the user.
35
XR16V2651
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE EFR[5]: Special Character Detect Enable
REV. 1.0.2
* Logic 0 = Special Character Detect Disabled (default). * Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with
data in Xoff-2 register. If a match exists, the receive data will be transferred to FIFO and ISR bit-4 will be set to indicate detection of the special character. Bit-0 corresponds with the LSB bit of the receive character. If flow control is set for comparing Xon1, Xoff1 (EFR [1:0]= `10') then flow control and special character work normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]= `01') then flow control works normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special character interrupt, if enabled via IER bit-5. EFR[6]: Auto RTS Flow Control Enable RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is selected, an interrupt will be generated when the receive FIFO is filled to the selected trigger level and RTS deasserts HIGH at the next upper trigger level. RTS# will return LOW when FIFO data falls below the next lower trigger level. The RTS# output must be asserted (LOW) before the auto RTS can take effect. RTS# pin will function as a general purpose output when hardware flow control is disabled.
* Logic 0 = Automatic RTS flow control is disabled (default). * Logic 1 = Enable Automatic RTS flow control.
EFR[7]: Auto CTS Flow Control Enable Automatic CTS Flow Control.
* Logic 0 = Automatic CTS flow control is disabled (default). * Logic 1 = Enable Automatic CTS flow control. Data transmission stops when CTS# input de-asserts HIGH.
Data transmission resumes when CTS# returns LOW. 4.14.1 Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Read/Write These registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2. For more details, see Table 8.
36
XR16V2651
REV. 1.0.2
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE TABLE 16: UART RESET CONDITIONS FOR CHANNEL A AND B
REGISTERS DLM, DLL DLD RHR THR IER FCR ISR LCR MCR LSR MSR SPR EFR XON1 XON2 XOFF1 XOFF2 I/O SIGNALS TX OP2# RTS# DTR# RXRDY# TXRDY# INT (IRQ#) HIGH HIGH HIGH HIGH HIGH LOW Three-State Condition (16 mode) HIGH (68 mode) RESET STATE DLM = 0x00 and DLL = 0x01. Only resets to these values during a power up. They do not reset when the Reset Pin is asserted. Bits 7-0 = 0x00 Bits 7-0 = 0xXX Bits 7-0 = 0xXX Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x01 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x60 Bits 3-0 = Logic 0 Bits 7-4 = Logic levels of the inputs inverted Bits 7-0 = 0xFF Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 RESET STATE
37
XR16V2651
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE
REV. 1.0.2
ABSOLUTE MAXIMUM RATINGS
Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation 7 Volts GND-0.3V to 7V -40o to +85oC -65o to +150oC 500 mW
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: 15%)
Thermal Resistance (32-QFN) Thermal Resistance (48-TQFP) theta-ja =33oC/W, theta-jc = 22oC/W theta-ja =59oC/W, theta-jc = 16oC/W
ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS TA = -40O TO +85OC, VCC IS 2.25V TO 3.6V
SYMBOL VILCK VIHCK VIL VIH VOL PARAMETER Clock Input Low Level Clock Input High Level Input Low Voltage Input High Voltage Output Low Voltage 0.4 VOH Output High Voltage 1.8 IIL IIH CIN ICC ISLEEP Input Low Leakage Current Input High Leakage Current Input Pin Capacitance Power Supply Current Sleep Current 10 10 5 1.5 15 10 10 5 2.5 30 2.0 LIMITS 2.5V MIN MAX -0.3 2.0 -0.3 1.8 0.4 VCC 0.5 5.5 LIMITS 3.3V MIN MAX -0.3 2.4 -0.3 2.0 0.6 VCC 0.7 5.5 0.4 UNITS V V V V V V V V uA uA pF mA uA Ext Clk = 2 MHz See Test 1 IOL = 6 mA IOL = 4 mA IOH = -4 mA IOH = -2 mA CONDITIONS
Test 1: The following inputs must remain steady at VCC or GND state to minimize sleep current: A0-A2, D0-D7, IOR#, IOW# (R/W#), CSA# (CS#), CSB# (A3) and all modem inputs. Also, RXA and RXB inputs must idle HIGH while asleep. Floating inputs may result in sleep currents in the mA range. For PowerSave, the UART internally isolates all of these inputs (except the modem inputs) therefore eliminating any unnecessary external buffers to keep the inputs steady. SEE"POWERSAVE FEATURE" ON PAGE 21.
38
XR16V2651
REV. 1.0.2
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE
AC ELECTRICAL CHARACTERISTICS UNLESS OTHERWISE NOTED: TA = -40O TO +85OC, VCC=2.25 - 3.63V, 70 PF LOAD WHERE APPLICABLE
SYMBOL XTAL1 ECLK TECLK TAS TAH TCS TRD TDY TRDV TDD TWR TDY TDS TDH TADS TADH TRWS TRDA TRDH TWDS TWDH TRWH TCSL TCSD TWDO TMOD TRSI TSSI TRRI PARAMETER UART Crystal Oscillator External Clock External Clock Time Period Address Setup Time (16 mode) Address Hold Time (16 mode) Chip Select Width (16 mode) IOR# Strobe Width (16 mode) Read Cycle Delay (16 mode) Data Access Time (16 mode) Data Disable Time (16 mode) IOW# Strobe Width (16 mode) Write Cycle Delay (16 mode) Data Setup Time (16 mode) Data Hold Time (16 mode) Address Setup (68 Mode) Address Hold (68 Mode) R/W# Setup to CS# (68 Mode) Read Data Access (68 mode) Read Data Disable (68 mode) Write Data Setup (68 mode) Write Data Hold (68 Mode) CS# De-asserted to R/W# De-asserted (68 Mode) CS# Width (68 Mode) CS# Cycle Delay (68 Mode) Delay From IOW# To Output Delay To Set Interrupt From MODEM Input Delay To Reset Interrupt From IOR# Delay From Stop To Set Interrupt Delay From IOR# To Reset Interrupt 10 3 5 40 40 50 50 50 1 45 40 40 10 3 0 0 0 35 25 10 3 5 35 35 50 50 50 1 45 10 0 0 40 40 40 35 25 35 35 10 3 0 0 0 30 25 LIMITS 2.5V 10% MIN MAX 32 50 7 0 0 35 35 35 30 25 LIMITS 3.3V 10% MIN MAX 24 64 UNIT MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Bclk ns
39
XR16V2651
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE AC ELECTRICAL CHARACTERISTICS UNLESS OTHERWISE NOTED: TA = -40O TO +85OC, VCC=2.25 - 3.63V, 70 PF LOAD WHERE APPLICABLE
SYMBOL TSI TINT TWRI TSSR TRR TWT TSRT TRST Bclk PARAMETER Delay From Stop To Interrupt Delay From Initial INT Reset To Transmit Start Delay From IOW# To Reset Interrupt Delay From Stop To Set RXRDY# Delay From IOR# To Reset RXRDY# Delay From IOW# To Set TXRDY# Delay From Center of Start To Reset TXRDY# Reset Pulse Width Baud Clock 40 8 LIMITS 2.5V 10% MIN MAX 45 24 45 1 45 45 8 40 16X or 8X or 4X of data rate 8 LIMITS 3.3V 10% MIN MAX 45 24 45 1 45 45 8 UNIT ns Bclk ns Bclk ns ns Bclk ns Hz
REV. 1.0.2
FIGURE 13. CLOCK TIMING
TECLK
TECH
TECL
VIH
External Clock
VIL
40
XR16V2651
REV. 1.0.2
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE
FIGURE 14. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A & B
IOW # Active T W DO RTS# DTR# Change of state Change of state
CD# CTS# DSR# T MO D INT
Change of state
Change of state T M OD
Active T RSI
Active
Active
IOR#
Active
Active
Active T M OD
RI#
Change of state
FIGURE 15. 16 MODE (INTEL) DATA BUS READ TIMING
A0-A2 TAS
Valid Address TAS
Valid Address
TCS CSA#/ CSB#
TAH
TCS
TAH
TDY TRD IOR# TDD Valid Data TDD Valid Data TRD
TRDV D0-D7
TRDV
RDTm
41
XR16V2651
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE FIGURE 16. 16 MODE (INTEL) DATA BUS WRITE TIMING
REV. 1.0.2
A0-A2 TAS
Valid Address TAS
Valid Address
TCS CSA#/ CSB#
TAH
TCS
TAH
TDY TWR IOW# TWR
TDS D0-D7 Valid Data
TDH
TDS Valid Data
TDH
16Write
FIGURE 17. 68 MODE (MOTOROLA) DATA BUS READ TIMING
A0-A2 TADS
Valid Address TCSL TADH
Valid Address
CS# TRWS TCSD
R/W#
TRWH
TRDA D0-D7 Valid Data
TRDH
Valid Data
68Read
42
XR16V2651
REV. 1.0.2
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE
FIGURE 18. 68 MODE (MOTOROLA) DATA BUS WRITE TIMING
A0-A2 TADS
Valid Address TCSL TADH
Valid Address
CS# TRWS TRWH TCSD
R/W#
TWDS D0-D7 Valid Data
T WDH Valid Data
68Write
FIGURE 19. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B
RX
Start Bit Stop Bit TSSR 1 Byte in RHR TSSR Active Data Ready TRR
D0:D7
D0:D7 TSSR 1 Byte in RHR TSSR Active Data Ready TRR
D0:D7 TSSR 1 Byte in RHR TSSR Active Data Ready TRR
INT
RXRDY#
IOR#
(Reading data out of RHR)
RXNFM
43
XR16V2651
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE FIGURE 20. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B
TX
Start Bit IER[1] enabled Stop Bit
REV. 1.0.2
D0:D7
D0:D7
D0:D7
ISR is read
ISR is read
ISR is read
INT*
TWRI TSRT TWRI TSRT TWRI TSRT
TXRDY#
TWT
TWT
TWT
IOW#
(Loading data into THR)
*INT is cleared when the ISR is read or when data is loaded into the THR.
TXNonFIFO
FIGURE 21. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A & B
Start Bit
RX
S D0:D7 Stop Bit
S D0:D7 T
D0:D7
TSSI
S D0:D7 T
S D0:D7 T S D0:D7 T
S D0:D7 T
RX FIFO drops below RX Trigger Level
INT
TSSR
RXRDY# First Byte is Received in RX FIFO IOR#
(Reading data out of RX FIFO)
RX FIFO fills up to RX Trigger Level or RX Data Timeout
FIFO Empties
TRRI
TRR
RXINTDMA#
44
XR16V2651
REV. 1.0.2
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE
FIGURE 22. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A & B
Start Bit Stop Bit S D0:D7 T
RX
S D0:D7
D0:D7
TSSI
S D0:D7 T
S D0:D7 T S D0:D7 T
S D0:D7 T
RX FIFO drops below RX Trigger Level
INT RX FIFO fills up to RX Trigger Level or RX Data Timeout RXRDY#
TSSR
FIFO Empties
TRRI
TRR
IOR#
(Reading data out of RX FIFO)
RXFIFODMA
FIGURE 23. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B
Start Bit Stop Bit Last Data Byte Transmitted S D0:D7 T S D0:D7 T TSI T S D0:D7 T S D0:D7 T ISR is read TSRT S D0:D7 T
TX FIFO Empty
TX
(Unloading) IER[1] enabled
S D0:D7 T ISR is read
INT*
TX FIFO fills up to trigger level TX FIFO drops below trigger level
TX FIFO Empty TWRI
TXRDY#
Data in TX FIFO
TWT
IOW#
(Loading data into FIFO)
*INT is cleared when the ISR is read or when TX FIFO fills up to the trigger level.
TXDMA#
45
XR16V2651
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE
REV. 1.0.2
FIGURE 24. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B
Start Bit Stop Bit Last Data Byte Transmitted D0:D7 S D0:D7 T S D0:D7 T S D0:D7 T S D0:D7 T ISR Read
TX
(Unloading) IER[1] enabled
S D0:D7 T S D0:D7 T ISR Read
TSRT
TSI
INT*
TX FIFO fills up to trigger level TWRI TX FIFO Full TX FIFO drops below trigger level At least 1 empty location in FIFO
TXRDY#
TWT
IOW#
(Loading data into FIFO)
*INT cleared when the ISR is read or when TX FIFO fills up to trigger level.
TXDMA
46
XR16V2651
REV. 1.0.2
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE
PACKAGE DIMENSIONS (32 PIN QFN - 5 X 5 X 0.9 mm)
Note: the actual center pad is metallic and the size (D2) is device-dependent with a typical tolerance of 0.3mm
Note: The control dimension is in millimeter. INCHES SYMBOL A A1 A3 D D2 b e L k MIN 0.031 0.000 0.006 0.193 0.138 0.007 MAX 0.039 0.002 0.010 0.201 0.150 0.012 MILLIMETERS MIN 0.80 0.00 0.15 4.90 3.50 0.18 MAX 1.00 0.05 0.25 5.10 3.80 0.30
0.0197 BSC 0.012 0.008 0.020 -
0.50 BSC 0.35 0.20 0.45 -
47
XR16V2651
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 mm)
D D1 36 25
REV. 1.0.2
37
24
D1
D
48
13
1 B A2 e
1 12
C Seating Plane A A1
L
Note: The control dimension is the millimeter column INCHES SYMBOL A A1 A2 B C D D1 e L a MIN 0.039 0.002 0.037 0.007 0.004 0.346 0.272 MAX 0.047 0.006 0.041 0.011 0.008 0.362 0.280 MILLIMETERS MIN 1.00 0.05 0.95 0.17 0.09 8.80 6.90 MAX 1.20 0.15 1.05 0.27 0.20 9.20 7.10
0.020 BSC 0.018 0 0.030 7
0.50 BSC 0.45 0 0.75 7
48
XR16V2651
REV. 1.0.2
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE
REVISION HISTORY
DATE June 2006 March 2007 May 2007 May 2007 REVISION P1.0.0 1.0.0 1.0.1 1.0.2 Preliminary Datasheet Final Datasheet. Updated AC Electrical Characteristics. Added "GND Center Pad" to pin description. Updated 32 pin QFN package dimensions drawing to show minimum "k" parameter. Updated "AC electrical characteristics" table and pin description table. DESCRIPTION
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2007 EXAR Corporation Datasheet May 2007. Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
49
XR16V2651
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE
REV. 1.0.2
TABLE OF CONTENTS
GENERAL DESCRIPTION ................................................................................................ 1
APPLICATIONS............................................................................................................................................... 1 FEATURES .................................................................................................................................................... 1
FIGURE 1. XR16V2651 BLOCK DIAGRAM ......................................................................................................................................... 1 FIGURE 2. PIN OUT ASSIGNMENT ..................................................................................................................................................... 2 ORDERING INFORMATION................................................................................................................................ 2
PIN DESCRIPTIONS ........................................................................................................ 3
1.0 PRODUCT DESCRIPTION....................................................................................................................... 7 2.0 FUNCTIONAL DESCRIPTIONS............................................................................................................... 8
2.1 CPU INTERFACE................................................................................................................................................. 8
FIGURE 3. XR16V2651 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS........................................................................... 8
2.2 5-VOLT TOLERANT INPUTS .............................................................................................................................. 2.3 DEVICE RESET ................................................................................................................................................... 2.4 DEVICE IDENTIFICATION AND REVISION........................................................................................................ 2.5 CHANNEL A AND B SELECTION.......................................................................................................................
8 9 9 9
TABLE 1: CHANNEL A AND B SELECT IN 16 MODE ............................................................................................................................ 9 TABLE 2: CHANNEL A AND B SELECT IN 68 MODE ............................................................................................................................ 9
2.6 DMA MODE........................................................................................................................................................ 10
TABLE 3: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE ........................................................................................... 10
2.7 INTA AND INTB OUTPUTS ............................................................................................................................... 10
TABLE 4: INTA AND INTB PINS OPERATION FOR TRANSMITTER ...................................................................................................... 10 TABLE 5: INTA AND INTB PIN OPERATION FOR RECEIVER ............................................................................................................. 10
2.8 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK INPUT .............................................................................. 11
FIGURE 4. TYPICAL CRYSTAL CONNECTIONS ................................................................................................................................... 11
2.9 PROGRAMMABLE BAUD RATE GENERATOR WITH FRACTIONAL DIVISOR............................................ 11
FIGURE 5. BAUD RATE GENERATOR ............................................................................................................................................... 12 TABLE 6: TYPICAL DATA RATES WITH A 24 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING ................................................... 13
2.10 TRANSMITTER ................................................................................................................................................ 13
2.10.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY ......................................................................................... 2.10.2 TRANSMITTER OPERATION IN NON-FIFO MODE .................................................................................................. FIGURE 6. TRANSMITTER OPERATION IN NON-FIFO MODE .............................................................................................................. 2.10.3 TRANSMITTER OPERATION IN FIFO MODE ........................................................................................................... FIGURE 7. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE ..................................................................................... 14 14 14 14 14
2.11 RECEIVER ....................................................................................................................................................... 15
2.11.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY ............................................................................................ 15 FIGURE 8. RECEIVER OPERATION IN NON-FIFO MODE .................................................................................................................... 15 FIGURE 9. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE ......................................................................... 16
2.12 AUTO RTS (HARDWARE) FLOW CONTROL ................................................................................................ 16 2.13 AUTO RTS HYSTERESIS............................................................................................................................... 17
TABLE 7: AUTO RTS (HARDWARE) FLOW CONTROL ........................................................................................................................ 17
2.14 AUTO CTS FLOW CONTROL ........................................................................................................................ 17
FIGURE 10. AUTO RTS AND CTS FLOW CONTROL OPERATION....................................................................................................... 18
2.15 AUTO XON/XOFF (SOFTWARE) FLOW CONTROL...................................................................................... 19
TABLE 8: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL ............................................................................................................... 19
2.16 SPECIAL CHARACTER DETECT .................................................................................................................. 19 2.17 INFRARED MODE ........................................................................................................................................... 20
FIGURE 11. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING .......................................................................... 20
2.18 SLEEP MODE WITH WAKE-UP INDICATOR AND POWERSAVE FEATURE............................................. 21
2.18.1 SLEEP MODE ............................................................................................................................................................. 21 2.18.2 POWERSAVE FEATURE............................................................................................................................................ 21
2.19 INTERNAL LOOPBACK ................................................................................................................................. 22
FIGURE 12. INTERNAL LOOP BACK IN CHANNEL A AND B ................................................................................................................ 22
3.0 UART INTERNAL REGISTERS ............................................................................................................. 23
TABLE 9: UART CHANNEL A AND B UART INTERNAL REGISTERS ....................................................................................... 23 TABLE 10: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1 ....................................... 24
4.0 INTERNAL REGISTER DESCRIPTIONS............................................................................................... 25
4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY .................................................................................. 25 4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................... 25 4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE................................................................................. 25
I
XR16V2651
REV. 1.0.2
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE
4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................... 25 4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION.................................................................. 26
4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY .................................................................................. 27
4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 27 4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. 27 TABLE 11: INTERRUPT SOURCE AND PRIORITY LEVEL ..................................................................................................................... 28
4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ........................................................................................ 28
TABLE 12: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION .......................................................................... 29
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE ........................................................................................ 29
TABLE 13: PARITY SELECTION ........................................................................................................................................................ 31
4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE . 4.8 LINE STATUS REGISTER (LSR) - READ ONLY.............................................................................................. 4.9 MODEM STATUS REGISTER (MSR) - READ ONLY ....................................................................................... 4.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE ....................................................................................... 4.11 BAUD RATE GENERATOR REGISTERS (DLL, DLM AND DLD) - READ/WRITE .......................................
31 32 33 34 34
TABLE 14: SAMPLING RATE SELECT ............................................................................................................................................... 34
4.12 DEVICE IDENTIFICATION REGISTER (DVID) - READ ONLY....................................................................... 34 4.13 DEVICE REVISION REGISTER (DREV) - READ ONLY................................................................................. 35 4.14 ENHANCED FEATURE REGISTER (EFR) ..................................................................................................... 35
TABLE 15: SOFTWARE FLOW CONTROL FUNCTIONS ........................................................................................................................ 35 4.14.1 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - READ/WRITE .............................. 36 TABLE 16: UART RESET CONDITIONS FOR CHANNEL A AND B ............................................................................................ 37
ABSOLUTE MAXIMUM RATINGS ................................................................................. 38 TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: 15%) 38 ELECTRICAL CHARACTERISTICS............................................................................... 38
DC ELECTRICAL CHARACTERISTICS............................................................................................................. 38
TA = -40o to +85oC, Vcc is 2.25V to 3.6V ............................................................................................................. 38
AC ELECTRICAL CHARACTERISTICS............................................................................................................. 39
Unless otherwise noted: TA = -40o to +85oC, Vcc=2.25 - 3.63V, 70 pF load where applicable.............................. 39
FIGURE 13. CLOCK TIMING............................................................................................................................................................. 40 FIGURE 14. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A & B ................................................................................................. 41 FIGURE 15. 16 MODE (INTEL) DATA BUS READ TIMING ................................................................................................................... 41 FIGURE 16. 16 MODE (INTEL) DATA BUS WRITE TIMING ................................................................................................................. 42 FIGURE 17. 68 MODE (MOTOROLA) DATA BUS READ TIMING .......................................................................................................... 42 FIGURE 18. 68 MODE (MOTOROLA) DATA BUS WRITE TIMING......................................................................................................... 43 FIGURE 19. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B ......................................................... 43 FIGURE 20. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B ....................................................... 44 FIGURE 21. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A & B........................................ 44 FIGURE 22. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A & B......................................... 45 FIGURE 23. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B ........................... 45 FIGURE 24. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B ............................ 46 PACKAGE DIMENSIONS (32 PIN QFN - 5 X 5 X 0.9 mm) ............................................................................... 47
PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 mm) .................................................................................. 48 REVISION HISTORY ..................................................................................................................................... 49 TABLE OF CONTENTS ..................................................................................................... I
II

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